This invention relates to static random access memory (xe2x80x9cSRAMxe2x80x9d) devices, and, more particularly, to a system and method for powering-up SRAM devices having PMOS access transistors to limit the initial current draw of such SRAM devices.
Many integrated circuit devices, such as microprocessors, include onboard memory devices, such as SRAM devices. For example, SRAM devices are commonly used as cache memory because of their relatively fast speed. SRAM devices are also sold as stand-alone integrated circuits for use as cache memory and for other uses. SRAM devices are also more suitable for use as cache memory than dynamic random access memory (xe2x80x9cDRAMxe2x80x9d) devices because they need not be refreshed, thus making all SRAM memory cells continuously available for a memory access.
FIG. 1 is a block diagram of a portion of a typical array 10 of SRAM cells 12 arranged in rows and columns. A plurality of complementary digit line pairs D, D* are used to couple complementary data to and from the memory cells 12 in a respective column. Several digit line pairs, typically 16 or 32 digit line pairs, are coupled to respective inputs of a column multiplexer 13. The column multiplexer 13 couples one pair of digit lines corresponding to a column address to a sense amplifier 14 and a write driver 16. The sense amplifer 14 provides a data output (not shown) indicative of the polarity of one digit line D relative to the other D* responsive to data being read from a memory cell 12 coupled to the selected digit line pair D, D*. The write driver 16 drives a differential voltage onto the digit lines D, D* to which the write driver 16 is coupled by the column multiplexer 13. The differential voltage applied between the digit lines is indicative of data that is to be written to a memory cell 12 coupled to the digit lines D, D*. An equilibration PMOS transistor 18 is also coupled between each pair of complementary digit lines D, D* to equalize the voltage between the digit lines D, D* prior to a memory read operation. Finally, a complementary PMOS bias transistor 20 is coupled to each digit line D, D* to lightly bias the digit lines D, D* to Vcc for reasons that will be explained. The current provided by each pair of bias transistors is controlled by a respective digit line load signal DLLN.
A plurality of word lines WL1-WL4 are used to activate the memory cells 12 in the respective row of memory cells. The word lines WL1-WL4 are coupled to a respective inverter 30 each formed by a PMOS transistor 34 and an NMOS transistor 36 coupled in series between Vcc and ground. The gates of the transistors 34, 36 are coupled to each other and to a respective select line SEL WL1-SEL WL4.
In a read operation, the digit lines D, D* for all columns are equilibrated by driving an EQ* line low. An inverter 30 then drives a word line WL1-WL4 in a single row to an appropriate voltage, thereby coupling a memory cell 12 in each column to a respective pair of digit lines D, D*. The memory cell 12 in each column unbalances the digit lines D, D* to which it is coupled, and the respective sense amplifier 14 senses the polarity of the unbalance and provides an appropriate data signal.
In a write operation, a suitable voltage is first applied to a word line WL1-WL4 to couple the memory cells 12 in the respective row to a digit line D or a complimentary digit line D*. The write driver 18 for one or more columns then applies a differential voltage between the digit lines D, D* for respective columns, which is coupled to respective memory cells 12 for the activated row. The write driver 18 is then disabled for a xe2x80x9crite recoveryxe2x80x9d phase, and the word line WL1-WL4 is then deactivated so the memory cell 12 stores the polarity of the differential voltage. The bias transistors 20 are provided for the array 10 regardless of the type of SRAM cell used. However, in the event the memory cells 12 are loadless 4T memory cells, which are discussed further below, the current provided by the bias transistors 20 allow the memory cells 12 to continue to store the data, as also discussed further below.
A typical memory cell shown in FIG. 2 is a conventional 6-transistor (6-T) SRAM cell 40. The SRAM cell 40 includes a pair of NMOS access transistors 42 and 44 that allow a differential voltage on the digit lines D, D*, to be read from and written to a storage circuit 50 of the SRAM cell 40. The storage circuit 50 includes NMOS pull-down transistors 52 and 56 that are coupled in a positive-feedback configuration with PMOS pull-up transistors 54 and 58, respectively. Nodes A and B are complementary inputs/output nodes of the storage circuit 50, and the respective complementary logic values at these nodes represent the state of the SRAM cell 40. For example, when the node A is at logic xe2x80x9c1xe2x80x9d and the node B is at logic xe2x80x9c0xe2x80x9d, then the SRAM cell 40 is storing a logic xe2x80x9c1xe2x80x9d. Conversely, when the node A is at logic xe2x80x9c0xe2x80x9d and the node B is at logic xe2x80x9c1xe2x80x9d, then the SRAM cell 40 is storing a logic xe2x80x9c0xe2x80x9d. Thus, the SRAM cell 40 is bistable, i.e., the SRAM cell 40 can have one of two stable states, logic xe2x80x9c1xe2x80x9d or logic xe2x80x9c0xe2x80x9d.
In operation during a read of the SRAM cell 40, a word-line WL, such as WL1-WL4 (FIG. 1), which is coupled to the gates of the access transistors 42 and 44, is driven to a voltage approximately equal to Vcc to turn ON the transistors 42 and 44. The access transistor 42 then couples the node A to the digit line D, and the access transistor 44 couples the node B to the digit line D*. Assuming the SRAM cell 40 is storing a logic xe2x80x9c0xe2x80x9d, coupling the digit line D to the node A pulls down the voltage on the digit line D enough (for example, 100-500 millivolts) to cause the sense amplifier 14 (FIG. 1) coupled between the digit lines D, D* to read the SRAM cell 40 as storing a logic xe2x80x9c0xe2x80x9d.
During a write operation of a logic xe2x80x9c1xe2x80x9d to the SRAM cell 40, for example, a logic xe2x80x9c1xe2x80x9d is applied to the digit lines D, D* as a differential voltage, and the word line WL is activated to turn ON the access transistors 42, 44. The transistor 42 then couples the logic xe2x80x9c1xe2x80x9d voltage of approximately Vcc to the node A, and the transistor 44 couples the logic xe2x80x9c0xe2x80x9d voltage of approximately ground to the node B. The word line WL is finally deactivated to turn OFF the access transistors 42, 44, thereby allowing the SRAM cell 40 to continue storing the logic xe2x80x9c1xe2x80x9d.
Although the 6-T cell 40 shown in FIG. 2 uses PMOS pull-up transistors 54, 58, it will be understood that other components (not shown), such as pull-up resistors (not shown), may be used in place of the pull-up transistors 54, 58.
Another typical SRAM cell is shown in FIG. 3. The SRAM cell shown in FIG. 3 is a conventional 4-transistor (4-T) loadless SRAM cell 60, where elements common to the SRAM cell 40 of FIG. 2 are referenced with like numerals or letters. The SRAM cell 60 is considered loadless because it uses a storage circuit 66 in which the loads formed by the pull-up transistors 54, 58 have been eliminated. Further, the NMOS access transistors 42 and 44 have been replaced with PMOS transistors 62 and 64, respectively. With the loadless 4-T SRAM cell 60 of FIG. 3, there are no pull-up transistors to maintain the drain of the OFF NMOS transistor 52, 56 at a voltage that is sufficient to turn ON the other NMOS transistor 52, 56. Instead, the access transistors 62, 64 are biased in their OFF states by conventional means with a voltage that causes leakage currents and/or subthreshold currents to be coupled from the digit lines D, D* through the access transistors 62, 64. These leakage currents and/or subthreshold currents maintain the voltage on the drain of the OFF NMOS transistor 52, 56, at a voltage that is sufficiently high to maintain the other NMOS transistor 52, 56 in an ON condition. In order to supply these leakage currents and/or subthreshold currents, the PMOS bias transistors 20 (FIG. 1) are controlled by the digit line load signals DLLN to supply currents to the digit lines D, D* when the memory cells 12 are not being accessed, as previously explained. However, the impedance of the transistors 20 must be sufficiently high that the digit lines D, D* in each pair can be driven low by the memory cells 12 and the write drivers 18.
The primary advantage of the 4-T SRAM cell 60 shown in FIG. 3 compared to the 6-T SRAM cell 40 shown in FIG. 2 is that the 4-T SRAM cell 60 uses only 4 transistors and is thus more compact. As a result, the 4-T SRAM cell 60 consumes less surface area on a semiconductor die.
Although the loadless 4T SRAM cell 60 of FIG. 3 has the advantage of being more compact, it also has some disadvantages compared to the 6-T SRAM cell 40 of FIG. 2. These disadvantages primarily result from the need to supply the correct amount of leakage and/or subthreshold current through the access transistors 62, 64, and the need to use PMOS access transistors 62, 64 rather than NMOS access transistors 42, 44. Too little leakage and/or subthreshold current supplied to the storage circuit 66 may cause a data retention failure. If too much leakage and/or subthreshold current is supplied to the storage circuit 66, then the standby current limits of an array using the SRAM cell 60 may be exceeded.
The primary advantage of the 4-T SRAM cell 60 shown in FIG. 3 compared to the 6-T SRAM cell 40 shown in FIG. 2 is that the 4-T SRAM cell 60 uses only 4 transistors and is thus more compact. As a result, the 4-T SRAM cell 60 consumes less surface area on a semiconductor die.
Although the loadless 4T SRAM cell 60 of FIG. 3 has the advantage of being more compact, it also has some disadvantages compared to the 6-T SRAM cell 40 of FIG. 2. These disadvantages primarily result from the need to supply the correct amount of leakage and/or subthreshold current through the access transistors 62, 64, and the need to use PMOS access transistors 62, 64 rather than NMOS access transistors 42, 44. Too little leakage and/or subthreshold current supplied to the storage circuit 66 may cause a data retention failure. If too much leakage and/or subthreshold current is supplied to the storage circuit 66, then the standby current limits of an array using the SRAM cell 60 may be exceeded.
Another problem resulting from the use of PMOS access transistors 62, 64 can be explained with reference also to FIG. 1. When power is initially applied to an integrated circuit containing the memory array 10, the digit lines D, D* can be driven to Vcc before the word lines WL1-WL4 are driven high. With reference to FIG. 3, if the digit lines D, D* are at a high voltage when the voltage on the word line WL is low, the access transistors 62, 64 will be turned ON, thereby coupling the storage cell 66 to the digit lines D, D*. In fact, all of the SRAM cells 60 in the array 10 will generally be coupled to their respective digit lines D, D* under these circumstances. Although the leakage and/or subthreshold current drawn by any single SRAM cell 60 will be very small, the total current drawn by all of the SRAM cells 60 can be very large. For example, for a read current of as little as 100 microamperes (10xe2x88x924 amperes), the total current drawn by a 4 megabit SRAM array during power-up would be 400 amperes (10xe2x88x924*4*106). Even though the current will not be this high in practice because of the finite current sourcing capability of the bias transistors 20, this amount of current is still far too much current to be drawn by SRAM memory devices.
Note that the problem of excessive currents at power-up does not exist for the 6-T SRAM cell 40 shown in FIG. 2 because the NMOS access transistors 42, 44 will be OFF if the voltages of the word lines WL are less than the voltages on the digit lines D, D*. However, although not commonly in use, there may be circuit designs in which excessive power-up currents could be a problem even with NMOS access transistors 42, 44.
There is therefore a need for a system and method to limit the current drawn by SRAM arrays during power-up, particularly for arrays of SRAM cells having PMOS access transistors, such as loadless 4-T SRAM cells.
An array of SRAM cells arranged in rows and columns includes a wordline for each row of the array and a pair of complementary digit lines for each column of the array. Each of the SRAM cells has a pair of access transistors coupled to respective complementary digit lines for a respective column and a gate coupled to a wordline for a respective row. A bias circuit coupled to each of the digit lines is operable in either a normal mode or a power-up mode. In the normal mode, the bias circuit couples a bias current to the digit lines. In the power-up mode, the bias circuit maintains the access transistors non-conductive.